Tight. 2 of 4 warning signs are red, 2 are unknown. Confidence: medium.
TSMC's CEO said in July: "Our packaging capacity is so tight that now it limits my customers' growth." TSMC forecasts its CoWoS capacity will grow more than 80% a year on average from 2022 to 2027, but demand keeps pace.
Outlook: TrendForce, a market research firm, expects the shortage to "begin to ease slightly by 2027," with CoWoS-L still the mainstream AI packaging through 2028. Alternatives like Intel's EMIB matter more after that. That's a forecast, not a measurement.
New here? Skip to Background below for the basics. Coming back? Start with What changed.
This month
October 2026 · Updated Oct 4 · Next update after TSMC's Oct 15 call
What changed since last month
First reading. From next month this section leads with what moved and why.
Scorecard
Warning sign | What we saw | Reading | Source |
Long waits | No current, reliable lead-time figure. The 52–78 week number still quoted comes from an early-2026 analysis, so we don't score it. | ⚪ Unknown | — |
Orders above supply | TSMC CEO C.C. Wei: "Our packaging capacity is so tight that now it limits my customers' growth." TrendForce said in September that TSMC capacity is still short of demand. | 🔴 Yes | |
Prices going up | No confirmed price increase on packaging. TSMC said nothing about packaging prices on its July call. TrendForce notes bigger interposers raise packaging cost per chip, which is a cost, not a price hike. | ⚪ Unknown | |
New capacity not enough | Even with TSMC planning over 60% more CoWoS capacity by 2027, TrendForce expects the "severe shortage" to ease only "slightly" by 2027. It says the shortage has spread to packaging equipment, substrates and materials. | 🔴 Yes |
Score: 2 red, 0 green, 0 mixed, 2 unknown = 🟠 Tight. Two unknowns, so confidence is medium.
Dates to watch
Oct 15: TSMC Q3 earnings call. Listen for a new CoWoS capacity number, any packaging price comment, and whether "tight" is still the word.
Oct 22 (expected): Intel results. Any confirmed EMIB packaging customers in production.
Oct 26 and Oct 29 (expected): Amkor (Oct 26) and ASE (Oct 29) results. Listen for AI packaging revenue and new orders.
"Expected" dates come from earnings calendars. The company hasn't announced them yet.
Status history
- Oct 2026: 🟠 Tight (2 red, 2 unknown), medium confidence. First reading.
Background
Reference. Updated when the facts change, not every month.
What it is
Most leading AI accelerators need their high-speed memory (HBM) sitting right beside the processor, wired together on one package. TSMC's CoWoS (Chip-on-Wafer-on-Substrate) family does this, and it's the main packaging for AI accelerators today. Chips designed around CoWoS can't ship without it. Many other chips, like phone processors, use different packaging.
There are three main versions, according to TSMC:
- CoWoS-S: chips sit on a silicon interposer, a thin silicon base with dense wiring and tiny vertical wires (TSVs) through it.
- CoWoS-R: uses an RDL interposer made of redistribution layers (fine wiring layers) instead of silicon.
- CoWoS-L: uses an RDL-based interposer with small embedded silicon bridges (LSI) where the highest-density connections are needed. This lets packages grow much larger than a single silicon interposer allows. NVIDIA's and AMD's biggest AI chips use CoWoS-L.
Where it sits: Processor made on a wafer (TSMC) → CoWoS: processor + HBM memory joined on an interposer → tested → mounted on a board → server rack → data center
That's why packaging capacity in Taiwan can decide how many accelerators reach data centers in a quarter.
When something is short, two things happen. The seller can charge more and stays fully booked. The buyer has orders it can't fill on time. Same shortage, opposite effect on the stock.
Why can't they just build more?
- The shortage has spread upstream. TrendForce says it now reaches packaging equipment, substrates and materials.
- Packages keep getting bigger. TrendForce reports that NVIDIA's Rubin package uses an interposer about 5.5 times the reticle size, the largest area a chipmaking tool can print in one exposure. Bigger interposers mean fewer packages per wafer, so each wafer of new capacity makes fewer chips than before.
- Bigger means more can go wrong. Large interposers are harder to keep flat and align, and one defect can waste an expensive processor plus several memory stacks.
How big is it, and how fast is it growing?
Measure | Number |
TSMC CoWoS capacity growth (TSMC forecast) | More than 80% a year on average, 2022–2027. |
TSMC capacity, end-2026 (investor estimates) | About 120,000–140,000 wafers a month. |
Outside packagers' CoWoS-type capacity (investor estimates) | About 50,000–60,000 wafers a month. The source adds this to TSMC's figure, but the process steps and units may not match, so we don't add them. |
Supply-demand gap (investor estimates) | About 20% in mid-2026, narrowing to about 10% by end-2026. |
2027 plan (TrendForce) | TSMC to expand CoWoS capacity by over 60%. |
TSMC doesn't publish CoWoS capacity, so the wafer figures are outside estimates.
Forecast demand by customer
Morgan Stanley's forecast for 2026, made in December 2025. It covers each customer's total CoWoS-type demand across TSMC and outside packagers, about 1 million wafers in all. It isn't TSMC's confirmed allocation, and a smaller share doesn't mean a customer is worse supplied relative to its needs.
Customer | Forecast demand | What it's for |
NVIDIA | ~595k wafers (~60%) | Blackwell and Rubin GPUs. About 510k forecast at TSMC and about 80k at Amkor and ASE/SPIL. |
Broadcom | ~150k (~15%) | Custom chips for Google, Meta, OpenAI |
AMD | ~105k (~11%) | MI-series GPUs |
Others | ~125k | Marvell (~55k), Amazon (~50k), MediaTek (~20k) |
Who wins, who waits
The effects below are our interpretation, not company statements.
Company | Likely effect | Why |
Wins | Owns most CoWoS capacity. Gross margin was 67.7% in Q2 2026. Even if alternatives ease the packaging squeeze, TSMC says that extra flexibility "will help TSMC's frontend wafer business growth," so relief isn't necessarily bad for TSMC overall. | |
Wins | Takes spillover work. Has a multi-year advanced packaging collaboration with NVIDIA, with a prepayment to be received in 2027. Computing revenue rose 20% on the quarter in Q2. | |
ASE (ASX) | Wins | Its SPIL unit is named by TrendForce as a beneficiary of spillover demand. |
Intel (INTC) | Possible winner | TrendForce expects Google to adopt Intel's EMIB-T packaging in 2027, and says AWS is testing it. That's prospective, not production, and TrendForce still sees CoWoS-L as mainstream through 2028. |
Mixed | The largest forecast demand, but packaging still paces its ramps. The same shortage also limits rivals. | |
Exposed | Their AI chips need CoWoS too. Whether each is short relative to its own needs isn't public. | |
SMCI, Dell, HPE, Foxconn, Quanta, Wistron | Exposed | Server and rack builders can only ship AI servers as fast as accelerators arrive. |
Mixed | GPU cloud renters. Scarce new chips can rent at a premium, which helps whoever already has them, but growth is paced by deliveries. | |
META, Microsoft, Google, Amazon, Oracle | Exposed | Their capex turns into working AI capacity more slowly, one reason they're pursuing their own chips and other packaging. |
The takeaway: packaging constrains accelerator growth. Alternatives and new capacity would help chip shipments, but their effect on packaging margins and on TSMC overall can differ.
The companies behind CoWoS
These suppliers gain from the build-out whether or not the shortage lasts. Check how much each depends on AI before treating it as a play.
- HBM memory: MU, SK hynix and Samsung. Every CoWoS AI package carries several memory stacks.
- Cutting and grinding machines: Disco (6146.T), a leading maker of the saws and grinders used to thin and cut these chips.
- Chip testing: Advantest (6857.T) makes testers that check AI chips before they ship.
- Substrates (the board-like base): Ibiden (4062.T), Unimicron and Kinsus.
When does it end, and what could replace it?
Factory construction isn't the same as production. New lines still need tools installed, processes qualified and customers to approve the output.
- End-2026: investor estimates see the supply gap narrowing to about 10%.
- 2027: TSMC plans over 60% more capacity. TrendForce expects only slight relief.
- Intel EMIB-T: Google expected to adopt in 2027, AWS testing (TrendForce). Not yet production.
- TSMC's own options: a bridge-style method built with Kinsus (reported July 2026), and CoPoS, which packages on large square panels instead of round wafers. Its pilot line was due mid-2026, with volume production expected in 2028–29.
- US plants: TSMC has announced US advanced packaging fabs but gave no firm timeline on its July call. ASE and Amkor have new plants finishing construction around 2028–2029, with qualified production after that.
What could go wrong for this view
- Capacity catches up. With 60%+ growth planned for 2027 and outside packagers adding volume, the gap could close faster than forecast.
- Alternatives scale. If EMIB and panel packaging ramp well, CoWoS demand could cool.
- AI demand dips. TSMC's CEO sees strong demand "to probably 2029, 2030," but added: "Whether in between there's a dip or not, I'm not very sure."
How to read a change
Good easing
Waits shrink because more packaging capacity came online, at TSMC or elsewhere, while orders stay strong. More accelerators ship.
Bad easing
Waits shrink because customers ordered less. It looks like relief, but it means AI spending is cooling.
To tell them apart, check orders and guidance, not just wait times.
What would change our view
- Gets tighter: TSMC confirms a packaging price increase, or a named customer says a launch slipped because of packaging.
- Gets easier (good): TSMC says capacity is catching up while still guiding higher.
- Gets easier (bad): waits shorten at the same time as TSMC, NVIDIA or hyperscalers cut forecasts.
- Shifts away: big customers confirm production moves to Intel EMIB.
Past scorecards
Each month the previous scorecard moves here, newest first.
- None yet. October 2026 is the first reading.
Evidence and sources
Company statements
- TSMC Q2 2026 call (Jul 16, 2026): C.C. Wei, "Our packaging capacity is so tight that now it limits my customers' growth"; on alternative packaging, "I welcome that additional flexibility in the market and so that will help TSMC's frontend wafer business growth"; gross margin 67.7%; no packaging price comment; demand strong "to probably 2029, 2030… Whether in between there's a dip or not, I'm not very sure"; US advanced packaging fabs planned, no firm timeline. Transcript
- TSMC 2024 annual report: CoWoS-S uses a silicon interposer; CoWoS-R an RDL interposer; CoWoS-L an "RDL-based interposer and embedded local silicon interconnect (LSI)." TSMC
- Amkor Q2 2026 call (Jul 27, 2026): revenue $1.9B, up 26%; computing revenue up 20% on the quarter; NVIDIA collaboration with "a prepayment that would basically be received in 2027." Transcript
Market research and estimates
- TrendForce (Sep 18, 2026): TSMC capacity in short supply; CoWoS-L the mainstream AI packaging through 2028; larger interposers raise packaging cost; Google expected to introduce EMIB-T in 2027, AWS testing. In Chinese. TrendForce
- TrendForce (Apr 30, 2026): "The shortage of CoWoS has persisted, extending upstream to production equipment and downstream to substrates, packaging materials"; SPIL and Amkor benefit from spillover; shortage to "begin to ease slightly by 2027," with TSMC expanding CoWoS capacity by over 60% by 2027. TrendForce
- TrendForce News (Jun 15, 2026): gap about 20% narrowing to about 10% by end-2026 (institutional investor estimates via Economic Daily News); TSMC 120–140k wafers a month in 2026 and 50–60k from outside packagers; TSMC's forecast of more than 80% CAGR from 2022 to 2027 (per Reuters). TrendForce News
- TrendForce (Apr 13, 2026): Rubin interposer about 5.5x reticle size; CoPoS timeline. TrendForce
- Morgan Stanley 2026 CoWoS demand forecast by customer, across TSMC and outside packagers (Dec 2025). 36Kr, Dec 4 2025
Reported, not confirmed by all parties
- TSMC's bridge-style program with Kinsus. TechTimes, Jul 30 2026
- ASE and Amkor long-term plant projects finishing 2028–2029. ASE · Amkor
- Where sources disagree: investor estimates see the gap narrowing sharply by end-2026. TrendForce expects only slight relief in 2027.
Words used on this page
- CoWoS (Chip-on-Wafer-on-Substrate): TSMC's family of methods for joining a processor and its memory side by side on an interposer.
- Interposer: the base layer the processor and memory sit on. It carries the wiring between them. It can be silicon (CoWoS-S) or built from redistribution layers (CoWoS-R and CoWoS-L).
- RDL (Redistribution Layer): fine layers of wiring that route signals between chips.
- LSI (Local Silicon Interconnect): small silicon bridges embedded in a CoWoS-L interposer for the densest connections.
- TSV (Through-Silicon Via): tiny vertical wires drilled through silicon so signals can pass up and down.
- Reticle: the largest area a chipmaking tool can print in one exposure. A "5.5x reticle" interposer is over five times that area.
- HBM (High Bandwidth Memory): stacked memory chips that sit right next to the AI processor.
- Yield: the share of finished parts that actually work.
- Substrate: the board-like layer under the interposer that connects to the rest of the server.
- EMIB (Embedded Multi-die Interconnect Bridge): Intel's method, using small silicon bridges in the package substrate where chips meet. EMIB-T adds TSVs.
- CoPoS (Chip-on-Panel-on-Substrate): TSMC's next method, using large square panels instead of round wafers.
- OSAT (Outsourced Semiconductor Assembly and Test): outside packaging firms like ASE and Amkor.
- CAGR (Compound Annual Growth Rate): the average yearly growth rate over several years.
- Qualified production: output that customers have tested and approved, as opposed to a line that is built but still ramping.
Invest Deeper · Educational research, not investment advice.
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